Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology

The demand of electronic product explodes in recent years, and the trend of electronic product is portable, multifunctional and budget currently. The fan-out wafer level packaging technology is a kind of wafer level packaging technology, and it becomes more and more attractive and popular because of...

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Main Author: Xu, Cheng
Other Authors: Zhong Zhaowei
Format: Theses and Dissertations
Language:English
Published: 2018
Subjects:
Online Access:http://hdl.handle.net/10356/75893
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-758932023-03-11T18:01:03Z Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology Xu, Cheng Zhong Zhaowei School of Mechanical and Aerospace Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging DRNTU::Engineering::Materials::Mechanical strength of materials The demand of electronic product explodes in recent years, and the trend of electronic product is portable, multifunctional and budget currently. The fan-out wafer level packaging technology is a kind of wafer level packaging technology, and it becomes more and more attractive and popular because of its flexibility to integrate diverse devices in a very small form factor. The fan-out wafer level packaging technology has the advantages of high density of input/output, minimal package size and low cost. The fan-out wafer level package (FOWLP) is usually used to volume sensitive devices such as mobile phones and wearables. However, the strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. Therefore, the study of strength behavior of FOWLP is essential. FOWLP is made up of various materials and thus the proper structure design and material selection are important to meet the reliability requirement. The FOWLP strength is evaluated by the experimental method and numerical method. We confirm three significant characteristics of FOWLP strength from the experimental work. The wafer grinding process, FOWLP dimension and thermal factor affect the FOWLP strength significantly. The numerical work proves that the flexure strength of over-molded structure FOWLP is higher than the flexure strength of other structure FOWLPs with the same package thickness. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point. The comparison of FOWLP strength model with experiment results and simulation results shows that they are identical. A new theoretical model of FOWLP fatigue crack growth is proposed. This model additionally considers the effect of thermal factor on the FOWLP fatigue crack growth. Doctor of Philosophy (MAE) 2018-07-15T10:36:27Z 2018-07-15T10:36:27Z 2018 Thesis Xu, C. (2018). Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology. Doctoral thesis, Nanyang Technological University, Singapore. http://hdl.handle.net/10356/75893 10.32657/10356/75893 en 216 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
DRNTU::Engineering::Materials::Mechanical strength of materials
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
DRNTU::Engineering::Materials::Mechanical strength of materials
Xu, Cheng
Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
description The demand of electronic product explodes in recent years, and the trend of electronic product is portable, multifunctional and budget currently. The fan-out wafer level packaging technology is a kind of wafer level packaging technology, and it becomes more and more attractive and popular because of its flexibility to integrate diverse devices in a very small form factor. The fan-out wafer level packaging technology has the advantages of high density of input/output, minimal package size and low cost. The fan-out wafer level package (FOWLP) is usually used to volume sensitive devices such as mobile phones and wearables. However, the strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. Therefore, the study of strength behavior of FOWLP is essential. FOWLP is made up of various materials and thus the proper structure design and material selection are important to meet the reliability requirement. The FOWLP strength is evaluated by the experimental method and numerical method. We confirm three significant characteristics of FOWLP strength from the experimental work. The wafer grinding process, FOWLP dimension and thermal factor affect the FOWLP strength significantly. The numerical work proves that the flexure strength of over-molded structure FOWLP is higher than the flexure strength of other structure FOWLPs with the same package thickness. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point. The comparison of FOWLP strength model with experiment results and simulation results shows that they are identical. A new theoretical model of FOWLP fatigue crack growth is proposed. This model additionally considers the effect of thermal factor on the FOWLP fatigue crack growth.
author2 Zhong Zhaowei
author_facet Zhong Zhaowei
Xu, Cheng
format Theses and Dissertations
author Xu, Cheng
author_sort Xu, Cheng
title Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
title_short Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
title_full Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
title_fullStr Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
title_full_unstemmed Advanced flip chip and wafer level packages for 2.5D and 3D IC package technology
title_sort advanced flip chip and wafer level packages for 2.5d and 3d ic package technology
publishDate 2018
url http://hdl.handle.net/10356/75893
_version_ 1761781157762957312