A high speed 16-bit CMOS multiplier IC design
In this project, various multiplication algorithms are investigated and used to implement 16-bit CMOS multiplier design. And some common adders are also studied and developed using Verilog HDL language. By using different combination of algorithm and adder, we will study the performance of each 1...
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| 主要作者: | |
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| 其他作者: | |
| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2018
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/76261 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In this project, various multiplication algorithms are investigated and used to
implement 16-bit CMOS multiplier design. And some common adders are also
studied and developed using Verilog HDL language. By using different
combination of algorithm and adder, we will study the performance of each 16-
bit multiplier design.
Vedic algorithm, Wallace tree algorithm and booth algorithm are proposed in
the project to implement 16-bit multiplication.
Functional model of all the 16-bit multiplier design were developed using
Verilog HDL language. The simulation using Verilog Complier was shown to
have successful multiplication function. And schematic was synthesized on
Design Vision in AMS 0.36um technology. |
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