An EScheduler-based data dependence analysis and task scheduling for parallel circuit simulation

• Main Authors: Chen, Xiaoming, Yu, Hao, Yang, Huazhong, Wu, Wei, Wang, Yu
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/79643; http://hdl.handle.net/10220/8748
• Institution: Nanyang Technological University

The sparse matrix solver has become the bottleneck in a Simulation Program with Integrated Circuit Emphasis circuit simulator. It is difficult to parallelize the sparse matrix solver because of the high data dependence during the numerical LU factorization. In this brief, a parallel LU factorization algorithm is developed on shared-memory computers with multicore central processing units, based on KLU algorithms. An Elimination Scheduler (EScheduler) is proposed to represent the data dependence during the LU factorization. Based on the EScheduler, the parallel tasks are scheduled in two modes to achieve a high level of concurrence, i.e., cluster mode and pipeline mode. The experimental results on 26 circuit matrices reveal that the developed algorithm can achieve speedup of 1.18–4.55× (on geometric average), as compared with KLU, with 1–8 threads. The result analysis indicates that for different data dependence, different parallel strategies should be dynamically selected to obtain optimal performance.