Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

In modern VLSI technology, the occurrence of all kinds of...

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Main Authors: Zhu, Ning, Goh, Wang Ling, Zhang, Weija, Yeo, Kiat Seng, Kong, Zhi Hui
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2010
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/79964
http://hdl.handle.net/10220/6241
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-79964
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spelling sg-ntu-dr.10356-799642020-03-07T13:57:22Z Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing Zhu, Ning Goh, Wang Ling Zhang, Weija Yeo, Kiat Seng Kong, Zhi Hui School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors. Published version 2010-04-30T06:54:26Z 2019-12-06T13:37:42Z 2010-04-30T06:54:26Z 2019-12-06T13:37:42Z 2009 2009 Journal Article Zhu, N., Goh, W. L., Zhang, W., Yeo, K. S., & Kong, Z. H. (2009). Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. pp, 1-5. 1063-8210 https://hdl.handle.net/10356/79964 http://hdl.handle.net/10220/6241 10.1109/TVLSI.2009.2020591 en IEEE transactions on very large scale integration (VLSI) systems 5 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Zhu, Ning
Goh, Wang Ling
Zhang, Weija
Yeo, Kiat Seng
Kong, Zhi Hui
Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Zhu, Ning
Goh, Wang Ling
Zhang, Weija
Yeo, Kiat Seng
Kong, Zhi Hui
format Article
author Zhu, Ning
Goh, Wang Ling
Zhang, Weija
Yeo, Kiat Seng
Kong, Zhi Hui
author_sort Zhu, Ning
title Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
title_short Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
title_full Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
title_fullStr Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
title_full_unstemmed Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
title_sort design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
publishDate 2010
url https://hdl.handle.net/10356/79964
http://hdl.handle.net/10220/6241
_version_ 1681040438503407616
description In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.

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