Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization
Performance of FPGA-based token dataflow architectures is often limited by the long tail distribution of parallelism in the compute paths of the dataflow graphs. This is known to limit speedup of dataflow processing of Sparse LU factorization to only 3-10x over CPUs. One reason behind the limitation...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/81207 http://hdl.handle.net/10220/39179 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Performance of FPGA-based token dataflow architectures is often limited by the long tail distribution of parallelism in the compute paths of the dataflow graphs. This is known to limit speedup of dataflow processing of Sparse LU factorization to only 3-10x over CPUs. One reason behind the limitations is the serialization penalty of processing high-fanout nodes in the dataflow graph on traditional dataflow processing architectures. In this paper, we show how to perform one-time static fanout decomposition and selective node replication transformations to input dataflow graphs. These transformations are one-time static compute costs that are typically amortized over millions of iterations. For dataflow graphs extracted for sparse LU factorization, we demonstrate up to 2.3x speedup (1.2x geomean average) with this technique across a range of benchmark problems. |
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