Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing

• Main Authors: Kapre, Nachiket, Chandrashekaran, Bibin, Ng, Harnhua, Teo, Kirvy
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 主題: Computer Science and Engineering
• 在線閱讀: https://hdl.handle.net/10356/81244; http://hdl.handle.net/10220/39167

Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics. In the...