Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing

• Main Authors: Kapre, Nachiket, Chandrashekaran, Bibin, Ng, Harnhua, Teo, Kirvy
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: Computer Science and Engineering
• Online Access: https://hdl.handle.net/10356/81244; http://hdl.handle.net/10220/39167
• Institution: Nanyang Technological University

Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics. In these circumstances, developers trying to close timing are either at the mercy of random trials through placement seed exploration or through vendor-provided design space exploration tools that run a few compilation trials with changes to the CAD tool options (or parameters). Instead, we propose evaluating multiple CAD runs in parallel on the cloud, supported by a Bayesian learning and classification framework for generating multiple CAD parameter combinations most likFPGA CAD tool parametersely to help attain timing closure. We maintain a database of FPGA CAD tool parameters (input) along with associated variations in timing slack (output)to enable the learning process. A key engineering resource we use here is cheap and abundant parallelism made possible through cloud computing frameworks such as the Google Compute Engine. Across a range of open-source benchmarks, we show that learning helps improve total negative slack (TNS) scores by 10.5× (geomean) when compared to a single baseline run of Quart us 14.1 and by 7× (geomean) when compared to Alter a Quart us 14.1 Design Space Explorer (DSE).