Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing

• المؤلفون الرئيسيون: Kapre, Nachiket, Chandrashekaran, Bibin, Ng, Harnhua, Teo, Kirvy
• مؤلفون آخرون: School of Computer Engineering
• التنسيق: Conference or Workshop Item
• اللغة: English
• منشور في: 2015
• الموضوعات: Computer Science and Engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/81244; http://hdl.handle.net/10220/39167

Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics. In the...