Evaluating the efficiency of DSP Block synthesis inference from flow graphs
The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applic...
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| المؤلفون الرئيسيون: | , |
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| مؤلفون آخرون: | |
| التنسيق: | Conference or Workshop Item |
| اللغة: | English |
| منشور في: |
2013
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| الوصول للمادة أونلاين: | https://hdl.handle.net/10356/83937 http://hdl.handle.net/10220/12874 |
| الوسوم: |
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| المؤسسة: | Nanyang Technological University |
| اللغة: | English |
| الملخص: | The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. |
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