Evaluating the efficiency of DSP Block synthesis inference from flow graphs
The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applic...
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sg-ntu-dr.10356-839372020-05-28T07:17:39Z Evaluating the efficiency of DSP Block synthesis inference from flow graphs Ronak, Bajaj.. Fahmy, Suhaib A. School of Computer Engineering International Conference on Field Programmable Logic and Applications (22nd : 2012 : Oslo, Norway) The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. 2013-08-02T04:08:22Z 2019-12-06T15:34:55Z 2013-08-02T04:08:22Z 2019-12-06T15:34:55Z 2012 2012 Conference Paper https://hdl.handle.net/10356/83937 http://hdl.handle.net/10220/12874 10.1109/FPL.2012.6339163 en |
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The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation. |
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School of Computer Engineering |
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School of Computer Engineering Ronak, Bajaj.. Fahmy, Suhaib A. |
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Conference or Workshop Item |
author |
Ronak, Bajaj.. Fahmy, Suhaib A. |
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Ronak, Bajaj.. Fahmy, Suhaib A. Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
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Ronak, Bajaj.. |
title |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
title_short |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
title_full |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
title_fullStr |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
title_full_unstemmed |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs |
title_sort |
evaluating the efficiency of dsp block synthesis inference from flow graphs |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/83937 http://hdl.handle.net/10220/12874 |
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1681056228001710080 |