Evaluating the efficiency of DSP Block synthesis inference from flow graphs

The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applic...

Full description

Saved in:
Bibliographic Details
Main Authors: Ronak, Bajaj.., Fahmy, Suhaib A.
Other Authors: School of Computer Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Online Access:https://hdl.handle.net/10356/83937
http://hdl.handle.net/10220/12874
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English

Similar Items