High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits

• Main Authors: Ho, Weng-Geng, Liu, Nan, Ne, Kyaw Zwa Lwin, Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2016
• 主題: Voltage stabilizing circuits; Asynchronous logic
• 在線閱讀: https://hdl.handle.net/10356/84007; http://hdl.handle.net/10220/41672
• 機構: Nanyang Technological University

We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Cond...