High Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits
We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Cond...
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Main Authors: | Ho, Weng-Geng, Liu, Nan, Ne, Kyaw Zwa Lwin, Chong, Kwen-Siong, Gwee, Bah Hwee, Chang, Joseph Sylvester |
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Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2016
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/84007 http://hdl.handle.net/10220/41672 |
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Institution: | Nanyang Technological University |
Language: | English |
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