A case for energy-efficient acceleration of graph problems using embedded FPGA-based SoCs

• Main Authors: Moorthy, Pradeep, Kapre, Nachiket
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2018
• Subjects: Energy Efficiency; Sparse Graphs; DRNTU::Engineering::Computer science and engineering
• Online Access: https://hdl.handle.net/10356/87968; http://hdl.handle.net/10220/45595
• Institution: Nanyang Technological University

Sparse graph problems are notoriously hard to accelerate on conventional platforms due to irregular memory access patterns resulting in underutilization of memory bandwidth. These bottlenecks on traditional x86-based systems mean that sparse graph problems scale very poorly, both in terms of performance and power efficiency. A cluster of embedded SoCs (systems-on-chip) with closely-coupled FPGA accelerators can support distributed memory accesses with better matched low-power processing. We first conduct preliminary experiments across a range of COTS (commercial off-the-shelf) embedded SoCs to establish promise for energy-efficiency acceleration of sparse problems. We select the Xilinx Zynq SoC with FPGA accelerators to construct a prototype 32-node Beowulf cluster. We develop specialized MPI routines and memory DMA offload engines to support irregular communication efficiently. In this setup, we use the ARM processor as a data marshaller for local DMA traffic as well as remote MPI traffic while the FPGA may be used as a programmable accelerator. Across a set of benchmark graphs, we show that 32-node embedded SoC cluster can exceed the energy efficiency of an Intel E5-2407 by as much as 1.7× at a total graph processing capacity of 91–95 MTEPS for graphs as large as 32 million nodes and edges.