Design and optimization of the extended true single-phase clock-based prescaler

• Main Authors: Yu, Xiao Peng, Do, Manh Anh, Lim, Wei Meng, Yeo, Kiat Seng, Ma, Jianguo
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/91419; http://hdl.handle.net/10220/5950

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed...