Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

• المؤلفون الرئيسيون: Sia, Choon Beng, Ong, Beng Hwee, Chan, Kwok Wai, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh
• مؤلفون آخرون: School of Electrical and Electronic Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2009
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/91514; http://hdl.handle.net/10220/4663
• المؤسسة: Nanyang Technological University

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-µm RFCMOS technology, experimental results in this...