Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

• Main Authors: Sia, Choon Beng, Ong, Beng Hwee, Chan, Kwok Wai, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/91514; http://hdl.handle.net/10220/4663
• 機構: Nanyang Technological University

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-µm RFCMOS technology, experimental results in this...