Temperature and stress distribution in the SOI structure during fabrication

• Main Authors: Tan, Cher Ming, Gan, Zhenghao, Gao, Xiaofang
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/91726; http://hdl.handle.net/10220/4654
• Institution: Nanyang Technological University

Silicon wafer bonding technology is becoming one of the key technologies in the silicon-on-insulator (SOI) structure fabrication. However, the high-temperature heat treatment during SOI fabrication is inevitable, and the thermal stress thus induced could have an adverse effect on the device fabricated and the bonding interface. In this work, a finite-element analysis software, ANSYS, is used to study the induced mechanical stresses at the interface during the withdrawal of wafers from a high-temperature furnace. It is found that the type of insulators and the geometric dimension of the devices such as the thickness of the work layer, insulator layer, and the substrate thickness are insignificant contributors to the induced thermal stresses. Although it is expected that the furnace temperature and withdrawal velocity are the key factors in determining the mechanical stresses, for the present bonding strength of wafers via wafer bonding technology, the withdrawal velocity must be less than 100 mm/min, and under such a withdrawal velocity, the furnace temperature is also an insignificant factor with regard to the induced stress.