Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power

• Main Authors: Yu, Hao, Shi, Yiyu, He, Lei, Karnik, Tanay
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/92285; http://hdl.handle.net/10220/6262
• Institution: Nanyang Technological University

The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126x faster to obtain temperature, and reduces the number of thermal vias by 2.04x under the same temperature bound.