A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector

• Main Authors: Tan, Yung Sern, Yeo, Kiat Seng, Boon, Chirn Chye, Do, Manh Anh
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/95912; http://hdl.handle.net/10220/11325
• Institution: Nanyang Technological University

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow U...