Perspective of flash memory realized on vertical Si nanowires

• Main Authors: Yu, Hongyu, Sun, Yuan, Singh, Navab, Lo, Guo-Qing, Kwong, Dim Lee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/96165; http://hdl.handle.net/10220/11120
• Institution: Nanyang Technological University

In this review article, the scaling challenges of planar non-volatile memory, especially the flash-types including both floating gate-based and charge-trap-based devices are firstly discussed. The promising prospects brought by 3-Dimensional (3-D) nano-wire-based cells have been presented along with various device demonstrations and discussions on vertical nano-wire platform. The memory devices with highly scaled single-crystal Si nanowire (SiNW) channel and a gate-all-around (GAA) structure achieve superior program/erase (P/E) speed, cycling and high-temperature retention characteristics as compared to the planar one and are considered as promising candidate for future ultra-high non-volatile flash memory application.