High-performance printed carbon nanotube thin-film transistors array fabricated by a nonlithography technique using hafnium oxide passivation layer and mask

• Main Authors: Raman Pillai, Suresh Kumar, Chan-Park, Mary B.
• Other Authors: School of Chemical and Biomedical Engineering
• Format: Article
• Language: English
• Published: 2013
• Online Access: https://hdl.handle.net/10356/96367; http://hdl.handle.net/10220/10245
• Institution: Nanyang Technological University

The large-scale application of semiconducting single-walled carbon nanotubes (s-SWCNTs) for printed electronics requires scalable, repeateable, as well as noncontaminating assembly techniques. Previously explored nanotube deposition methods include serial methods such as inkjet printing and parallel methods such as spin-coating with photolithography. The serial methods are usually slow, whereas the photolithography-related parallel methods result in contamination of the nanotubes. In this paper, we report a reliable clean parallel method for fabrication of arrays of carbon nanotube-based field effect transistors (CNTFETs) involving shadow mask patterning of a passivating layer of Hafnium oxide (HfO2) over the nanotube (CNT) active channel regions and plasma etching of the unprotected nanotubes. Pure (99%) semiconducting SWCNTs are first sprayed over the entire surface of a wafer substrate followed by a two-step shadow masking procedure to first deposit metal electrodes and then a HfO2 isolation/passivation layer over the device channel region. The exposed SWCNT network outside the HfO2 protected area is removed with oxygen plasma etching. The HfO2 thus serves as both the device isolation mask during the plasma etching and as a protective passivating layer in subsequent use. The fabricated devices on SiO2/Si substrate exhibit good device performance metrics, with on/off ratio ranging from 1 × 101 to 3 × 105 and mobilities of 4 to 23 cm2/(V s). The HfO2/Si devices show excellent performance with on/off ratios of 1 × 102 to 2 × 104 and mobilities of 8 to 56 cm2/(V s). The optimum devices (on HfO2/Si) have an on/off ratio of 1 × 104 and mobility as high as 46 cm2/(V s). This HfO2-based patterning method enables large scale fabrication of CNTFETs with no resist residue or other contamination on the device channel. Further, shadow masking circumvents the need for expensive and area-limited lithography patterning process. The device channel is also protected from external environment by the HfO2 film and the passivated device shows similar (or slightly improved) performance after 300 days of exposure to ambient conditions.