GaN-on-Silicon integration technology

• Main Authors: Ng, Geok Ing, Arulkumaran, Subramaniam, Vicknesh, Sahmuganathan, Wang, H., Ang, K. S., Kumar, C. M. Manoj, Ranjan, K., Lo, Guo-Qiang, Tripathy, Sudhiranjan, Boon, Chirn Chye, Lim, Wei Meng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2013
• 在線閱讀: https://hdl.handle.net/10356/98842; http://hdl.handle.net/10220/12826

This work presents our recent progress on addressing two major challenges to realizing GaN-Silicon integration namely epitaxial growth of GaN-on-Silicon and CMOS-compatible process. We have successfully demonstrated 0.3-μm gate-length GaN HEMTs on 8-inch Si(111) substrate with fT of 28GHz and fmax of of 64GHz. These device performances are comparable to our reported devices fabricated on 4-inch Si substrate. We have also developed a GaN HEMT process with CMOS-compatible non-gold metal scheme. Excellent ohmic contacts (Rc=0.24 Ω-mm) with smooth surface morphology have been achieved which are comparable to those using conventional III-V gold-based ohmic contacts. 0.15-μm gate-length GaN HEMTs fabricated with this process achieved fT and fmax of 51 GHz and 50GHz respectively. The 5nm-thick AlGaN barrier HEMT exhibited three terminal OFF-state breakdown voltage (BVgd) of 83 V. Our results demonstrate the feasibility of realizing CMOS-compatible high performance GaN HEMTs on 8-inch silicon substrates for future GaN-on-Si integration.