Maximization of SRAM energy efficiency utilizing MTCMOS technology
Higher-Vth devices in the cross-coupled latches and the write access transistors, and lower-Vth devices in the read ports are preferred for reducing leakage current without sacrificing performance. However, at ultra-low supply voltage levels, higher-Vth devices can retard or nullify energy efficienc...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/99114 http://hdl.handle.net/10220/12584 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Higher-Vth devices in the cross-coupled latches and the write access transistors, and lower-Vth devices in the read ports are preferred for reducing leakage current without sacrificing performance. However, at ultra-low supply voltage levels, higher-Vth devices can retard or nullify energy efficiency due to substantially slower write speed than read. This paper presents energy efficiency maximization techniques for 8T SRAMs utilizing multi-threshold CMOS (MTCMOS) technology and various design techniques. Simulation results using a commercial 65 nm technology show that the SRAM energy efficiency can improved up to 33x through MTCMOS and prior power reduction and performance boosting techniques. |
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