Proposed FPGA hardware architecture for high frame rate (>100 fps) face detection using feature cascade classifiers
10.1109/BTAS.2007.4401930
Saved in:
Main Authors: | Lai H.-C., Savvides M., Chen T. |
---|---|
Other Authors: | OFFICE OF THE PROVOST |
Format: | Conference or Workshop Item |
Published: |
2018
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/146261 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Communication-aware face detection using noc architecture
by: Lai H.-C., et al.
Published: (2018) -
Cascade of classifiers to classify interictal EEGs of patients with epilepsy
by: Jiang, Zhubo
Published: (2018) -
In system programming of FPGA without hardware intervention
by: Yang, Zhiren
Published: (2013) -
Comparison between GPU and FPGA as hardware accelerator
by: Yang, Lu
Published: (2014) -
Quantum correction hardware accelerator design on FPGA
by: Cao, Hongyu
Published: (2023)