Simulation of board level drop test for wafer level packages
Master's
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2010
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sg-nus-scholar.10635-151542024-10-25T14:08:12Z Simulation of board level drop test for wafer level packages GU JIE MECHANICAL ENGINEERING LIM CHWEE TECK TAY AH ONG, ANDREW electronic package, drop test, modeling and simulation Master's MASTER OF ENGINEERING 2010-04-08T10:50:35Z 2010-04-08T10:50:35Z 2005-12-25 Thesis GU JIE (2005-12-25). Simulation of board level drop test for wafer level packages. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/15154 NOT_IN_WOS en |
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National University of Singapore |
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NUS Library |
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Asia |
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Singapore Singapore |
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ScholarBank@NUS |
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English |
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electronic package, drop test, modeling and simulation |
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electronic package, drop test, modeling and simulation GU JIE Simulation of board level drop test for wafer level packages |
description |
Master's |
author2 |
MECHANICAL ENGINEERING |
author_facet |
MECHANICAL ENGINEERING GU JIE |
format |
Theses and Dissertations |
author |
GU JIE |
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GU JIE |
title |
Simulation of board level drop test for wafer level packages |
title_short |
Simulation of board level drop test for wafer level packages |
title_full |
Simulation of board level drop test for wafer level packages |
title_fullStr |
Simulation of board level drop test for wafer level packages |
title_full_unstemmed |
Simulation of board level drop test for wafer level packages |
title_sort |
simulation of board level drop test for wafer level packages |
publishDate |
2010 |
url |
http://scholarbank.nus.edu.sg/handle/10635/15154 |
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1821211309958496256 |