Simulation of board level drop test for wafer level packages

Master's

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Bibliographic Details
Main Author: GU JIE
Other Authors: MECHANICAL ENGINEERING
Format: Theses and Dissertations
Language:English
Published: 2010
Subjects:
Online Access:http://scholarbank.nus.edu.sg/handle/10635/15154
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Institution: National University of Singapore
Language: English
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spelling sg-nus-scholar.10635-151542024-10-25T14:08:12Z Simulation of board level drop test for wafer level packages GU JIE MECHANICAL ENGINEERING LIM CHWEE TECK TAY AH ONG, ANDREW electronic package, drop test, modeling and simulation Master's MASTER OF ENGINEERING 2010-04-08T10:50:35Z 2010-04-08T10:50:35Z 2005-12-25 Thesis GU JIE (2005-12-25). Simulation of board level drop test for wafer level packages. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/15154 NOT_IN_WOS en
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
language English
topic electronic package, drop test, modeling and simulation
spellingShingle electronic package, drop test, modeling and simulation
GU JIE
Simulation of board level drop test for wafer level packages
description Master's
author2 MECHANICAL ENGINEERING
author_facet MECHANICAL ENGINEERING
GU JIE
format Theses and Dissertations
author GU JIE
author_sort GU JIE
title Simulation of board level drop test for wafer level packages
title_short Simulation of board level drop test for wafer level packages
title_full Simulation of board level drop test for wafer level packages
title_fullStr Simulation of board level drop test for wafer level packages
title_full_unstemmed Simulation of board level drop test for wafer level packages
title_sort simulation of board level drop test for wafer level packages
publishDate 2010
url http://scholarbank.nus.edu.sg/handle/10635/15154
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