Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

• Main Authors: Fong, Xuanyao, Choday, Sri Harsha, Roy, Kaushik
• Other Authors: DEPT OF ELECTRICAL & COMPUTER ENGG
• Format: Article
• Language: English
• Published: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2019
• Subjects: Science & Technology; Technology; Physical Sciences; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Materials Science, Multidisciplinary; Physics, Applied; Engineering; Science & Technology - Other Topics; Materials Science; Physics; Circuit optimization; magnetic memories; magnetic tunnel junctions (MTJ); memory architectures; spin-transfer torque MRAM (STT-MRAM) bit-cells
• Online Access: https://scholarbank.nus.edu.sg/handle/10635/156164
• Institution: National University of Singapore

10.1109/TNANO.2011.2169456