Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

10.1109/TNANO.2011.2169456

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Bibliographic Details
Main Authors:	Fong, Xuanyao, Choday, Sri Harsha, Roy, Kaushik
Other Authors:	DEPT OF ELECTRICAL & COMPUTER ENGG
Format:	Article
Language:	English
Published:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2019
Subjects:	Science & Technology Technology Physical Sciences Engineering, Electrical & Electronic Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Engineering Science & Technology - Other Topics Materials Science Physics Circuit optimization magnetic memories magnetic tunnel junctions (MTJ) memory architectures spin-transfer torque MRAM (STT-MRAM) bit-cells
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/156164
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-156164
record_format	dspace
spelling	sg-nus-scholar.10635-1561642023-09-21T08:49:16Z Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching Fong, Xuanyao Choday, Sri Harsha Roy, Kaushik DEPT OF ELECTRICAL & COMPUTER ENGG Science & Technology Technology Physical Sciences Engineering, Electrical & Electronic Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Engineering Science & Technology - Other Topics Materials Science Physics Circuit optimization magnetic memories magnetic tunnel junctions (MTJ) memory architectures spin-transfer torque MRAM (STT-MRAM) bit-cells 10.1109/TNANO.2011.2169456 IEEE TRANSACTIONS ON NANOTECHNOLOGY 11 1 172-181 2019-07-03T02:49:14Z 2019-07-03T02:49:14Z 2012-01-01 2019-07-03T02:40:43Z Article Fong, Xuanyao, Choday, Sri Harsha, Roy, Kaushik (2012-01-01). Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching. IEEE TRANSACTIONS ON NANOTECHNOLOGY 11 (1) : 172-181. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2011.2169456 1536125X 19410085 https://scholarbank.nus.edu.sg/handle/10635/156164 en IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC Elements
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
language	English
topic	Science & Technology Technology Physical Sciences Engineering, Electrical & Electronic Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Engineering Science & Technology - Other Topics Materials Science Physics Circuit optimization magnetic memories magnetic tunnel junctions (MTJ) memory architectures spin-transfer torque MRAM (STT-MRAM) bit-cells
spellingShingle	Science & Technology Technology Physical Sciences Engineering, Electrical & Electronic Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Engineering Science & Technology - Other Topics Materials Science Physics Circuit optimization magnetic memories magnetic tunnel junctions (MTJ) memory architectures spin-transfer torque MRAM (STT-MRAM) bit-cells Fong, Xuanyao Choday, Sri Harsha Roy, Kaushik Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
description	10.1109/TNANO.2011.2169456
author2	DEPT OF ELECTRICAL & COMPUTER ENGG
author_facet	DEPT OF ELECTRICAL & COMPUTER ENGG Fong, Xuanyao Choday, Sri Harsha Roy, Kaushik
format	Article
author	Fong, Xuanyao Choday, Sri Harsha Roy, Kaushik
author_sort	Fong, Xuanyao
title	Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
title_short	Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
title_full	Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
title_fullStr	Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
title_full_unstemmed	Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
title_sort	bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching
publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
publishDate	2019
url	https://scholarbank.nus.edu.sg/handle/10635/156164
_version_	1778169135394455552

Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

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