A RECONFIGURABLE PIPELINED PROCESSOR FOR REAL TIME IMAGE PROCESSING
Master's
Saved in:
主要作者: | GOH WEI CHUAN |
---|---|
其他作者: | ELECTRICAL ENGINEERING |
格式: | Theses and Dissertations |
出版: |
2020
|
在線閱讀: | https://scholarbank.nus.edu.sg/handle/10635/174712 |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
相似書籍
-
Opportunistic design margining for area and power efficient processor pipelines in real time applications
由: Jayakrishnan, Mini, et al.
出版: (2018) -
A pipelined educational simulator for the ARM processor
由: Chia, Belinda Wei Qi
出版: (2022) -
Design and implementation of a reconfigurable fuzzy inference processor
由: Cao, Qi
出版: (2008) -
Windows CE for a reconfigurable system-on-a-chip processor
由: George, M.R., et al.
出版: (2013) -
PARTIALLY RECONFIGURABLE HETEROGENEOUS MULTI-PROCESSOR SYSTEMS ON-CHIP
由: NGUYEN DUY ANH TUAN
出版: (2017)