Method for forming self-aligned elevated transistor

US6326272

Saved in:

Bibliographic Details
Main Authors:	CHAN, LAP, CHA, CHER LIANG
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Patent
Published:	2012
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/32604
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

id	sg-nus-scholar.10635-32604
record_format	dspace
spelling	sg-nus-scholar.10635-326042015-07-29T07:03:44Z Method for forming self-aligned elevated transistor CHAN, LAP CHA, CHER LIANG ELECTRICAL & COMPUTER ENGINEERING CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (SINGAPORE, SG) NATIONAL UNIVERSITY OF SINGAPORE US6326272 Granted Patent 2012-05-02T02:27:40Z 2012-05-02T02:27:40Z 2001-12-04 Patent CHAN, LAP,CHA, CHER LIANG (2001-12-04). Method for forming self-aligned elevated transistor. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/32604 NOT_IN_WOS PatSnap
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	US6326272
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING CHAN, LAP CHA, CHER LIANG
format	Patent
author	CHAN, LAP CHA, CHER LIANG
spellingShingle	CHAN, LAP CHA, CHER LIANG Method for forming self-aligned elevated transistor
author_sort	CHAN, LAP
title	Method for forming self-aligned elevated transistor
title_short	Method for forming self-aligned elevated transistor
title_full	Method for forming self-aligned elevated transistor
title_fullStr	Method for forming self-aligned elevated transistor
title_full_unstemmed	Method for forming self-aligned elevated transistor
title_sort	method for forming self-aligned elevated transistor
publishDate	2012
url	http://scholarbank.nus.edu.sg/handle/10635/32604
_version_	1681081253757976576

Similar Items