Method of fabricating a CMOS device with dual metal gate electrodes
US7316950
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2012
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Online Access: | http://scholarbank.nus.edu.sg/handle/10635/32753 |
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sg-nus-scholar.10635-327532024-11-14T01:25:08Z Method of fabricating a CMOS device with dual metal gate electrodes PARK, CHANG SEO CHO, BYUNG JIN BALASUBRAMANIAN, NARAYANAN T. ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE US7316950 Granted Patent 2012-05-02T02:29:53Z 2012-05-02T02:29:53Z 2008-01-08 Patent PARK, CHANG SEO,CHO, BYUNG JIN,BALASUBRAMANIAN, NARAYANAN T. (2008-01-08). Method of fabricating a CMOS device with dual metal gate electrodes. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/32753 NOT_IN_WOS PatSnap |
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US7316950 |
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ELECTRICAL & COMPUTER ENGINEERING |
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ELECTRICAL & COMPUTER ENGINEERING PARK, CHANG SEO CHO, BYUNG JIN BALASUBRAMANIAN, NARAYANAN T. |
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Patent |
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PARK, CHANG SEO CHO, BYUNG JIN BALASUBRAMANIAN, NARAYANAN T. |
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PARK, CHANG SEO CHO, BYUNG JIN BALASUBRAMANIAN, NARAYANAN T. Method of fabricating a CMOS device with dual metal gate electrodes |
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PARK, CHANG SEO |
title |
Method of fabricating a CMOS device with dual metal gate electrodes |
title_short |
Method of fabricating a CMOS device with dual metal gate electrodes |
title_full |
Method of fabricating a CMOS device with dual metal gate electrodes |
title_fullStr |
Method of fabricating a CMOS device with dual metal gate electrodes |
title_full_unstemmed |
Method of fabricating a CMOS device with dual metal gate electrodes |
title_sort |
method of fabricating a cmos device with dual metal gate electrodes |
publishDate |
2012 |
url |
http://scholarbank.nus.edu.sg/handle/10635/32753 |
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1821233783200808960 |