Global optimization for digital MOS circuits performance
10.1109/43.822628
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sg-nus-scholar.10635-505652023-08-29T08:44:49Z Global optimization for digital MOS circuits performance Chen, H.M. Samudra, G.S. Chan, D.S.H. Ibrahim, Y. ELECTRICAL ENGINEERING INDUSTRIAL & SYSTEMS ENGINEERING 10.1109/43.822628 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 1 161-164 ITCSD 2014-04-23T02:59:50Z 2014-04-23T02:59:50Z 2000 Article Chen, H.M., Samudra, G.S., Chan, D.S.H., Ibrahim, Y. (2000). Global optimization for digital MOS circuits performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 (1) : 161-164. ScholarBank@NUS Repository. https://doi.org/10.1109/43.822628 02780070 http://scholarbank.nus.edu.sg/handle/10635/50565 000085524500013 Scopus |
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ELECTRICAL ENGINEERING |
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ELECTRICAL ENGINEERING Chen, H.M. Samudra, G.S. Chan, D.S.H. Ibrahim, Y. |
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Chen, H.M. Samudra, G.S. Chan, D.S.H. Ibrahim, Y. |
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Chen, H.M. Samudra, G.S. Chan, D.S.H. Ibrahim, Y. Global optimization for digital MOS circuits performance |
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Chen, H.M. |
title |
Global optimization for digital MOS circuits performance |
title_short |
Global optimization for digital MOS circuits performance |
title_full |
Global optimization for digital MOS circuits performance |
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Global optimization for digital MOS circuits performance |
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Global optimization for digital MOS circuits performance |
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global optimization for digital mos circuits performance |
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2014 |
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http://scholarbank.nus.edu.sg/handle/10635/50565 |
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