A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs

• Main Authors: Loke, W.T., Ha, Y., Zhao, W.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Subjects: Dual-VT; EDA; FPGA; Programmable-VT; Reverse Back Bias; Technology Mapping
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/69009
• Institution: National University of Singapore

10.1109/IPDPSW.2012.23