TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

10.1109/ASPDAC.2013.6509615

Saved in:
Bibliographic Details
Main Authors: Haque, M.S., Kumar, A., Ha, Y., Wu, Q., Luo, S.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/72088
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore
Description
Summary:10.1109/ASPDAC.2013.6509615

Similar Items