TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

10.1109/ASPDAC.2013.6509615

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Bibliographic Details
Main Authors:	Haque, M.S., Kumar, A., Ha, Y., Wu, Q., Luo, S.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/72088
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-72088
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spelling	sg-nus-scholar.10635-720882015-01-06T05:12:53Z TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs Haque, M.S. Kumar, A. Ha, Y. Wu, Q. Luo, S. ELECTRICAL & COMPUTER ENGINEERING 10.1109/ASPDAC.2013.6509615 Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 320-325 2014-06-19T03:31:18Z 2014-06-19T03:31:18Z 2013 Conference Paper Haque, M.S.,Kumar, A.,Ha, Y.,Wu, Q.,Luo, S. (2013). TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 320-325. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ASPDAC.2013.6509615" target="_blank">https://doi.org/10.1109/ASPDAC.2013.6509615</a> 9781467330299 http://scholarbank.nus.edu.sg/handle/10635/72088 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	10.1109/ASPDAC.2013.6509615
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Haque, M.S. Kumar, A. Ha, Y. Wu, Q. Luo, S.
format	Conference or Workshop Item
author	Haque, M.S. Kumar, A. Ha, Y. Wu, Q. Luo, S.
spellingShingle	Haque, M.S. Kumar, A. Ha, Y. Wu, Q. Luo, S. TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
author_sort	Haque, M.S.
title	TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
title_short	TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
title_full	TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
title_fullStr	TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
title_full_unstemmed	TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
title_sort	trishul: a single-pass optimal two-level inclusive data cache hierarchy selection process for real-time mpsocs
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/72088
_version_	1681087501922467840

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

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