TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

• Main Authors: Haque, M.S., Kumar, A., Ha, Y., Wu, Q., Luo, S.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/72088
• Institution: National University of Singapore

10.1109/ASPDAC.2013.6509615