New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

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Bibliographic Details
Main Authors: Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F.
Other Authors: ELECTRICAL ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/81583
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Institution: National University of Singapore