New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

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Bibliographic Details
Main Authors:	Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F.
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/81583
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-81583
record_format	dspace
spelling	sg-nus-scholar.10635-815832015-01-08T16:34:27Z New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F. ELECTRICAL ENGINEERING Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 89-93 234 2014-10-07T03:09:51Z 2014-10-07T03:09:51Z 1999 Conference Paper Jie, B.B.,Li, M.F.,Chim, W.K.,Chan, D.S.H.,Lo, K.F. (1999). New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 89-93. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/81583 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F.
format	Conference or Workshop Item
author	Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F.
spellingShingle	Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F. New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
author_sort	Jie, B.B.
title	New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
title_short	New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
title_full	New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
title_fullStr	New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
title_full_unstemmed	New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
title_sort	new dc voltage-voltage method to measure the interface traps in deep sub-micron mos transistors
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/81583
_version_	1681089097653813248

New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors

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