New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Saved in:
Bibliographic Details
Main Authors: Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F.
Other Authors: ELECTRICAL ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/81583
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: National University of Singapore

Similar Items