50-250 MHz ΔΣ DLL for clock synchronization

• Main Authors: Cheng, S.-J., Qiu, L., Zheng, Y., Heng, C.-H.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Subjects: anti-harmonic detector; Clock synchronization; delay-locked loop (DLL); delta-sigma modulation; digital-to-phase converter; low jitter; second order adaptive filter
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/83302
• Institution: National University of Singapore

10.1109/JSSC.2010.2072591