Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance

10.1109/IEDM.2006.346840

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Bibliographic Details
Main Authors:	Singh, N., Lim, F.Y., Fang, W.W., Rustagi, S.C., Bera, L.K., Agarwal, A., Tung, C.H., Hoe, K.M., Omampuliyur, S.R., Tripathi, D., Adeyeye, A.O., Lo, G.Q., Balasubramanian, N., Kwong, D.L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/84334
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-84334
record_format	dspace
spelling	sg-nus-scholar.10635-843342015-01-08T00:43:15Z Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance Singh, N. Lim, F.Y. Fang, W.W. Rustagi, S.C. Bera, L.K. Agarwal, A. Tung, C.H. Hoe, K.M. Omampuliyur, S.R. Tripathi, D. Adeyeye, A.O. Lo, G.Q. Balasubramanian, N. Kwong, D.L. ELECTRICAL & COMPUTER ENGINEERING 10.1109/IEDM.2006.346840 Technical Digest - International Electron Devices Meeting, IEDM - TDIMD 2014-10-07T04:51:30Z 2014-10-07T04:51:30Z 2006 Conference Paper Singh, N.,Lim, F.Y.,Fang, W.W.,Rustagi, S.C.,Bera, L.K.,Agarwal, A.,Tung, C.H.,Hoe, K.M.,Omampuliyur, S.R.,Tripathi, D.,Adeyeye, A.O.,Lo, G.Q.,Balasubramanian, N.,Kwong, D.L. (2006). Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. Technical Digest - International Electron Devices Meeting, IEDM : -. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/IEDM.2006.346840" target="_blank">https://doi.org/10.1109/IEDM.2006.346840</a> 1424404398 01631918 http://scholarbank.nus.edu.sg/handle/10635/84334 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	10.1109/IEDM.2006.346840
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Singh, N. Lim, F.Y. Fang, W.W. Rustagi, S.C. Bera, L.K. Agarwal, A. Tung, C.H. Hoe, K.M. Omampuliyur, S.R. Tripathi, D. Adeyeye, A.O. Lo, G.Q. Balasubramanian, N. Kwong, D.L.
format	Conference or Workshop Item
author	Singh, N. Lim, F.Y. Fang, W.W. Rustagi, S.C. Bera, L.K. Agarwal, A. Tung, C.H. Hoe, K.M. Omampuliyur, S.R. Tripathi, D. Adeyeye, A.O. Lo, G.Q. Balasubramanian, N. Kwong, D.L.
spellingShingle	Singh, N. Lim, F.Y. Fang, W.W. Rustagi, S.C. Bera, L.K. Agarwal, A. Tung, C.H. Hoe, K.M. Omampuliyur, S.R. Tripathi, D. Adeyeye, A.O. Lo, G.Q. Balasubramanian, N. Kwong, D.L. Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
author_sort	Singh, N.
title	Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
title_short	Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
title_full	Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
title_fullStr	Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
title_full_unstemmed	Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
title_sort	ultra-narrow silicon nanowire gate-all-around cmos devices: impact of diameter, channel-orientation and low temperature on device performance
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/84334
_version_	1681089599415255040

Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance

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