V t balancing and device sizing towards high yield of sub-threshold static logic gates

V t balancing and device sizing towards high yield of sub-threshold static logic gates

10.1145/1283780.1283857

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Bibliographic Details
Main Authors: Pu, Y., De Gyvez, J.P., Corporaal, H., Ha, Y.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Subjects:
Sub-threshold
Variability
Online Access:http://scholarbank.nus.edu.sg/handle/10635/84346
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Institution: National University of Singapore

Internet

http://scholarbank.nus.edu.sg/handle/10635/84346

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