V t balancing and device sizing towards high yield of sub-threshold static logic gates

V t balancing and device sizing towards high yield of sub-threshold static logic gates

10.1145/1283780.1283857

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書目詳細資料
Main Authors:	Pu, Y., De Gyvez, J.P., Corporaal, H., Ha, Y.
其他作者:	ELECTRICAL & COMPUTER ENGINEERING
格式:	Conference or Workshop Item
出版:	2014
主題:	Sub-threshold Variability
在線閱讀:	http://scholarbank.nus.edu.sg/handle/10635/84346
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	National University of Singapore

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