V t balancing and device sizing towards high yield of sub-threshold static logic gates

10.1145/1283780.1283857

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Bibliographic Details
Main Authors:	Pu, Y., De Gyvez, J.P., Corporaal, H., Ha, Y.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Subjects:	Sub-threshold Variability
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/84346
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-84346
record_format	dspace
spelling	sg-nus-scholar.10635-843462024-11-12T01:20:37Z V t balancing and device sizing towards high yield of sub-threshold static logic gates Pu, Y. De Gyvez, J.P. Corporaal, H. Ha, Y. ELECTRICAL & COMPUTER ENGINEERING Sub-threshold Variability 10.1145/1283780.1283857 Proceedings of the International Symposium on Low Power Electronics and Design 355-358 2014-10-07T04:51:38Z 2014-10-07T04:51:38Z 2007 Conference Paper Pu, Y.,De Gyvez, J.P.,Corporaal, H.,Ha, Y. (2007). V t balancing and device sizing towards high yield of sub-threshold static logic gates. Proceedings of the International Symposium on Low Power Electronics and Design : 355-358. ScholarBank@NUS Repository. <a href="https://doi.org/10.1145/1283780.1283857" target="_blank">https://doi.org/10.1145/1283780.1283857</a> 1595937099 15334678 http://scholarbank.nus.edu.sg/handle/10635/84346 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Sub-threshold Variability
spellingShingle	Sub-threshold Variability Pu, Y. De Gyvez, J.P. Corporaal, H. Ha, Y. V t balancing and device sizing towards high yield of sub-threshold static logic gates
description	10.1145/1283780.1283857
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Pu, Y. De Gyvez, J.P. Corporaal, H. Ha, Y.
format	Conference or Workshop Item
author	Pu, Y. De Gyvez, J.P. Corporaal, H. Ha, Y.
author_sort	Pu, Y.
title	V t balancing and device sizing towards high yield of sub-threshold static logic gates
title_short	V t balancing and device sizing towards high yield of sub-threshold static logic gates
title_full	V t balancing and device sizing towards high yield of sub-threshold static logic gates
title_fullStr	V t balancing and device sizing towards high yield of sub-threshold static logic gates
title_full_unstemmed	V t balancing and device sizing towards high yield of sub-threshold static logic gates
title_sort	v t balancing and device sizing towards high yield of sub-threshold static logic gates
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/84346
_version_	1821205636104323072

V t balancing and device sizing towards high yield of sub-threshold static logic gates

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