Parameter synthesis for hierarchical concurrent real-time systems
Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is thus interesting to reason parametrically, by considering...
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| Main Authors: | , , , |
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| Format: | text |
| Language: | English |
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Institutional Knowledge at Singapore Management University
2014
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| Subjects: | |
| Online Access: | https://ink.library.smu.edu.sg/sis_research/4980 https://ink.library.smu.edu.sg/context/sis_research/article/5983/viewcontent/André2014_Article_ParameterSynthesisForHierarchi.pdf |
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| Institution: | Singapore Management University |
| Language: | English |
| Summary: | Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is thus interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesizing a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed Communicating Sequential Processes, a language capable of specifying and verifying parametric hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present several semi-algorithms for efficient parameter synthesis, which behave well in practice. This work has been implemented in a real-time model checker, PSyHCoS, and validated on a set of case studies. |
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