Modeling and verifying hierarchical real-time systems using stateful timed CSP

Modeling and verifying hierarchical real-time systems using stateful timed CSP

Modeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a langu...

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書目詳細資料
Main Authors:	SUN, Jun, LIU, Yang, DONG, Jin Song, LIU, Yan, SHI, Ling, ANDRÉ, Étienne
格式:	text
語言:	English
出版:	Institutional Knowledge at Singapore Management University 2013
主題:	Algorithms Languages Verification Programming Languages and Compilers Software Engineering
在線閱讀:	https://ink.library.smu.edu.sg/sis_research/4995 https://ink.library.smu.edu.sg/context/sis_research/article/5998/viewcontent/2430536.2430537.pdf
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