Realizing live sequence charts in system verilog
The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specied as scenarios of behavior using seque...
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| Main Authors: | , , , |
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| Format: | text |
| Language: | English |
| Published: |
Institutional Knowledge at Singapore Management University
2007
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| Subjects: | |
| Online Access: | https://ink.library.smu.edu.sg/sis_research/5054 https://ink.library.smu.edu.sg/context/sis_research/article/6057/viewcontent/realizing.pdf |
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| Institution: | Singapore Management University |
| Language: | English |
| Summary: | The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specied as scenarios of behavior using sequence charts for different use cases. This specication must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, Live Sequence Charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specications. |
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