Realizing live sequence charts in system verilog

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specied as scenarios of behavior using seque...

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Main Authors: WANG, Hai H., QIN, Shengchao, SUN, Jun, DONG, Jin Song
Format: text
Language:English
Published: Institutional Knowledge at Singapore Management University 2007
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Online Access:https://ink.library.smu.edu.sg/sis_research/5054
https://ink.library.smu.edu.sg/context/sis_research/article/6057/viewcontent/realizing.pdf
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spelling sg-smu-ink.sis_research-60572020-03-12T07:59:02Z Realizing live sequence charts in system verilog WANG, Hai H. QIN, Shengchao SUN, Jun DONG, Jin Song The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specied as scenarios of behavior using sequence charts for different use cases. This specication must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, Live Sequence Charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specications. 2007-08-06T07:00:00Z text application/pdf https://ink.library.smu.edu.sg/sis_research/5054 info:doi/10.1109/TASE.2007.41 https://ink.library.smu.edu.sg/context/sis_research/article/6057/viewcontent/realizing.pdf http://creativecommons.org/licenses/by-nc-nd/4.0/ Research Collection School Of Computing and Information Systems eng Institutional Knowledge at Singapore Management University Software Engineering
institution Singapore Management University
building SMU Libraries
continent Asia
country Singapore
Singapore
content_provider SMU Libraries
collection InK@SMU
language English
topic Software Engineering
spellingShingle Software Engineering
WANG, Hai H.
QIN, Shengchao
SUN, Jun
DONG, Jin Song
Realizing live sequence charts in system verilog
description The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specied as scenarios of behavior using sequence charts for different use cases. This specication must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, Live Sequence Charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specications.
format text
author WANG, Hai H.
QIN, Shengchao
SUN, Jun
DONG, Jin Song
author_facet WANG, Hai H.
QIN, Shengchao
SUN, Jun
DONG, Jin Song
author_sort WANG, Hai H.
title Realizing live sequence charts in system verilog
title_short Realizing live sequence charts in system verilog
title_full Realizing live sequence charts in system verilog
title_fullStr Realizing live sequence charts in system verilog
title_full_unstemmed Realizing live sequence charts in system verilog
title_sort realizing live sequence charts in system verilog
publisher Institutional Knowledge at Singapore Management University
publishDate 2007
url https://ink.library.smu.edu.sg/sis_research/5054
https://ink.library.smu.edu.sg/context/sis_research/article/6057/viewcontent/realizing.pdf
_version_ 1770575200997343232