Novel techniques for fully-intergrated RF CMOS phase-locked loop frequency synthesizer

by Boon, Chirn Chye.
Published 2008

An in-phase-coupled class-C quadrature VCO with tunable phase error

by Zhang, Yuxiang, Boon, Chirn Chye
Published 2015

A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

by Liang, Yuan, Boon, Chirn Chye
Published 2022

A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications

by Sunny, Sharma, Chen, Yong, Boon, Chirn Chye
Published 2019

Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology

by Liu, Hang, Zhu, Xi, Boon, Chirn Chye
Published 2015

A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain

by Yi, Xiang, Liang, Zhipeng, Boon, Chirn Chye
Published 2018

A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

by Balachandran, Arya, Chen, Yong, Boon, Chirn Chye
Published 2020

A crosstalk-immune sub-THz All-surface-wave I/O transceiver in 65-nm CMOS

by Liang, Yuan, Boon, Chirn Chye, Yu, Hao
Published 2020

A 40 GHz on-chip power combine load for mm-wave power amplifier

by Lin, Jiafu, Zhang, Gary, Boon, Chirn Chye
Published 2020

A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS

by Chen, Qian, Liang, Yuan, Boon, Chirn Chye
Published 2020

A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector

by Liang, Yuan, Boon, Chirn Chye, Chen, Qian
Published 2022

A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS

by Chen, Qian, Boon, Chirn Chye, Liang, Yuan
Published 2023

0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss

by Boon, Chirn Chye, Balachandran, Arya, Chen, Yong, Choi, Pilsoon
Published 2019

A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique

by Liang, Zhipeng, Yi, Xiang, Yang, Kaituo, Boon, Chirn Chye
Published 2019

A W-band switch-less Dicke receiver for millimeter-wave imaging in 65nm CMOS

by Feng, Guangyin, Yi, Xiang, Meng, Fanyi, Boon, Chirn Chye
Published 2018

A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter

by Chen, Qian, Liang, Yuan, Kim, Bongjin, Boon, Chirn Chye
Published 2020

A 20-80 MHz continuously tunable Gm-C low-pass filter for ultra-low power WBAN receiver front-end

by Wang, Xiaoying, Boon, Chirn Chye, Yang, Kaituo, Kong, Lingshan
Published 2022

A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS

by Chen, Qian, Boon, Chirn Chye, Liu, Qing, Liang, Yuan
Published 2023

17.8 A single-channel 10GS/s 8b>36.4d8 SNDR time-domain ADC featuring loop-unrolled asynchronous successive approximation in 28nm CMOS

by Chen, Qian, Liang, Yuan, Boon, Chirn Chye, Liu, Qing
Published 2023

A dual-path subsampling PLL with ring VCO phase noise suppression

by Dong, Yangtao, Boon, Chirn Chye, Liu, Zhe, Yang, Kaituo
Published 2023