DLS565: Design and characterization of a phase locked loop using 0.5um technology
Saved in:
Main Authors: | Atendido, Kenneth Martin C., Co, Justin Daniel C., Garcia, Pamela Candice H., Navarro, Gianmarco B. |
---|---|
Format: | text |
Language: | English |
Published: |
Animo Repository
2014
|
Subjects: | |
Online Access: | https://animorepository.dlsu.edu.ph/etd_bachelors/13333 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | De La Salle University |
Language: | English |
Similar Items
-
Full-custom design and characterization of a phase locked loop - DLS565 using 0.5um CMOS technology
by: Atendido, Kenneth Martin C., et al.
Published: (2014) -
DLS7555: Design and characterization of a 555 timer IC using 0.5um CMOS technology
by: Azares, Danica B., et al.
Published: (2014) -
Phase-locked loop for low frequency application using 0.18um CMOS technology
by: Zhang, Yao.
Published: (2009) -
0.5um EEPROM CHARACTERIZATION
by: SEOW KIAN CHIEW
Published: (2019) -
Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process
by: Escano, Ron Alvin V., et al.
Published: (2010)